This invention relates generally to comparator circuits and, more particularly, to an improved latching comparator circuit with hysteresis suitable for manufacture in integrated circuit form.
Differential comparator circuits for providing output level signals indicative of the magnitude of an input differential signal supplied thereto and having differential-to-single ended converter circuits associated therewith are well known in the art. Exemplary are those described in U.S. Pat. Nos. 3,649,846 and 3,872,323.
Generally, it is desirable to have zero input offset voltage so that as the magnitude of the differential input signal passes through the zero threshold level either in a positive or a negative sense, the output of the comparator circuit switches between two output level states. However, some comparator circuits are utilized in a high noise environment where relatively high noise transients may be generated. For example, if a noise transient occurs at or near the time that the differential input signal crosses through the zero threshold level, the output of the comparator circuit can be caused to erroneously switch output states due solely to the noise transient.
To overcome the problems associated with noise, some comparator circuits employ hysteresis which is generated internal to the comparator circuit itself. One such circuit is shown and described in U.S. Pat. No. 3,848,139 filed Sept. 14, 1973 issued Nov. 12, 1974 and entitled "High-Gain Comparator Circuit". Another such circuit is shown and described in copending U.S. Pat. No. 4,406,955 issued Sept. 27, 1983 entitled "Comparator Circuit Having Hysteresis" and assigned to the assignee of, the present invention. Unfortunately, these circuits suffer several disadvantages. First, no means are provided to prevent the current mirrors from saturating and such saturation will reduce the switching speed of the circuit and cause increased currents to flow in the substrate. Second, the output(s) is (are) taken from the collector(s) of the current mirror transistors which loads the input differential transistor pair and causes a loss of control of the hysteresis.